1. Field of the Invention
The present invention relates to a method for setting a pixel clock. In particular, the present invention discloses a method for setting a pixel clock used by a display controller.
2. Description of the Prior Art
With popularization of computer devices, associated computer technology has been quickly developed to improve functionality and convenience of computer devices. Recently, operating speed of a central processing unit (CPU) has already exceeded one gigahertz (GHz), and the computer devices have powerful data processing capability now. Therefore, normal users do not merely view the computer devices as great helpers for work. The computer device increasingly becomes one of the entertainment facilities at home. In addition, with development and application of well-known multimedia technology, monitors and graphics cards of computer devices responsible for outputting videos become a major factor when consumers purchase computer devices. Generally speaking, in order to conform to a plug and play (PNP) specification, the monitor has a display data channel (DDC) used to establish communication between a host of the computer device and the monitor of the computer device. That is, the monitor is capable of directly transferring its own hardware specification to the graphics card within the host. Therefore, the graphics card then acknowledges the hardware specification of the monitor. For example, the hardware specification includes maximum horizontal scanning frequency, the maximum vertical refresh rate, etc.
In the past, graphics cards of different brands had different settings for display modes of the monitor. Therefore, a compatibility problem existed among the graphics cards. For instance, an application established an interface between the application and hardware of the graphics card through instructions defined in a basic input/output system (BIOS) of the graphics card. However, with regard to different graphics cards, instructions defined in the basic input/output systems of these different graphics cards are not compatible. Therefore, the application was not capable of being applied to different graphics cards successfully. Finally, a video electronic standards association (VESA) defines a VESA bios extension (VBE) used to unify instructions within BIOS of the graphics card. In addition, the BIOS further records different display mode settings supported by the graphics card. Each display mode setting includes display information such as a horizontal scanning frequency, a vertical refresh rate, resolution, and gray levels for pixels.
Please refer to FIG. 1, which is a block diagram of a prior art computer device 10. The computer device 10 includes a central processing unit (CPU) 12, a memory 14, a chipset 15, a display driving circuit 16, and a display device 18 such as a monitor. The computer device 10 loads an operating system 20 into the memory 14 through a power-on-self-test (POST) procedure. Then, the chipset 15 is further actuated to coordinate data access for controlling operation of the computer device 10. The display driving circuit 16 is used to drive a plurality of pixels 22 positioned at the display device 18 so as to show a corresponding image. When a user adjusts a display mode setting related to the display device 18 through the operating system 20. The display driving circuit 16 used to drive the display device 18 resets a pixel clock according to the above-mentioned VBE specification. The pixel clock is used to control timing of setting gray level of each pixel. For example, suppose the user sets the resolution of display device 18 to be 1024×768. It is well-known that the display device 18 actually scans its screen (1360×802 for example) greater than the desired display area 1024×768 set by the user. If the user sets the vertical refresh rate associated with the display mode (1024×768) to be 60 Hz through the operating system 20. The frequency of desired pixel clock is equal to 1360*802*60 Hz, that is, 65443200 Hz.
The principal of the above operation is briefly described as follows. One frame shown on the display device 18 contains 1360*802 pixels needed to be scanned, and the vertical refresh rate is 60 Hz which means that 60 frames are scanned every one second. Therefore, gray levels of 655443200 pixels are set in one second. However, with regard to the display driving circuit 16, a hardware circuit such as a clock generator 24 is utilized to set the wanted pixel clock. Because the clock generator 24 is not capable of precisely generating the pixel clock with the required frequency (65443200 Hz), a basic input/output system 26 of the display driving circuit 16 needs to perform a clock setting procedure 28 for controlling the clock generator 24 to output a clock signal with a frequency approaching 65443200 Hz. Then, the outputted clock signal is adopted to be an actual pixel clock of the display driving circuit 16. The clock generator 24 generates the actual pixel clock according to a reference clock outputted from an oscillator 30.
As mentioned above, the clock generator 24 of the display driving circuit 16 cannot produce a predetermined pixel clock calculated according to a display mode. It is well-known the display driving circuit 16 has to generate the actual pixel clock approaching the predetermined pixel clock according to hardware specification of the clock generator 24. Generally speaking, the commonly used clock generator includes circuit components such as a frequency divider, a phase lock loop, etc., for generating the actual pixel clock based on the reference clock outputted from the oscillator 30. The oscillator 30 can be a crystal oscillator used to generate the reference clock with frequency equaling 14.318 megahertz (MHz), and inputs the reference clock into the clock generator 24. In other words, the actual pixel clock CLKcal is equal to a product calculated from the reference clock CLKref multiplied by result of a predetermined formula (M+2)/[(N+2)*2R].
The prior art process of setting the pixel clock, that is, execution of the clock setting procedure 28 is illustrated in the flow chart shown in FIG. 2. First, an initial value MINn is assigned to a value N (step 102). Then, the value N is checked to determine whether the value N is less than a threshold value MAXn (step 104). Step 104 is mainly used to determine if loop operations corresponding to the value N are finished. If the value N is greater than the threshold value MAXn, the loop operation associated with the value N is terminated, and then the clock generator 24 starts setting the pixel clock (step 136). On the contrary, if the value N is less than the threshold value MAXn, an initial value MINm is assigned to a value M (step 106). Then, the value M is checked to determine whether the value M is less than a threshold value MAXm (step 108). Similarly, step 108 is used to check if loop operations associated with the value M are finished. If the value M is greater than the threshold value MAXm, the loop operations corresponding to the value M are terminated, and the value N is then increased by 1 (step 110). On the contrary, if the value M is less than the threshold value MAXm, the reference clock CLKref is multiplied by a scaling factor to produce a product Vco (step 112). The scaling factor is represented by (M+2)/(N+2). Referring to the predetermined formula (M+2)/[(N+2)*2R], it is obvious that the calculated product Vco should be divided by 2R. Therefore, after step 112 has been completed, an initial value MINr is assigned to a value R (step 114), and the value R is checked to determine if the value R is less than a threshold value MAXr (step 116). Step 116 is used to check whether loop operations associated with the value R are finished. If the value R is greater than the threshold value MAXr, the loop operations corresponding to the value R are terminated, and the value M is increased by 1 (step 118). On the contrary, if the value R is less than the threshold value MAXr, a calculation result CLKcal is calculated from dividing the product Vco by a divisor 2R (step 120).
The calculation result is one candidate of the actual pixel clock. Therefore, a following comparing procedure is activated to judge the calculation result. It is first checked to see if values M, N, R are respectively equal to initial values MINm, MINn, MINr. If the values M, N, R respectively equal initial values MINm, MINn, MINr, the calculation result CLKcal calculated from step 120 is a first result outputted by the prior art clock setting procedure. Therefore, the calculation result CLKcal is an initial value of an optimum calculation result CLKbest (step 130). On the contrary, if values M, N, R are not respectively equal to initial values MINm, MINn, MINr, the calculation result CLKcal and a predetermined pixel clock CLKp are used to calculate a first difference D1 (step 124), and a second difference D2 is calculated according to the optimum calculation result CLKbest and the predetermined pixel clock CLKp (step 126). Finally, a check is done to determine if the first difference D1 is less than the second difference D2 (step 128). If the first difference D1 is less than the second difference D2, it means that the calculation result CLKcal is less than the currently recorded optimum calculation result CLKbest. Then, value of the calculation result CLKcal updates the optimum calculation result CLKbest (step 130). At the same time, values M, N, R corresponding to the optimum calculation result CLKbest are recorded, and then the value R is increased by 1. The clock setting procedure then jumps to step 106 for continuously performing following loop operations associated with the value R. On the contrary, if the first difference D1 is greater than the second difference D2, it means that the currently recorded optimum calculation result CLKbest is less than the calculation result CLKcal, and the optimum calculation result CLKbest holds its value without being updated. Similarly, the value R is increased by 1, and the prior art clock setting procedure jumps to step 116 for performing following loop operations associated with the value R.
The prior art clock setting procedure contains loop operations respectively corresponding values M, N, R. After the three loop operations are completed, it means that the prior art clock setting procedure totally calculates 128*128*128 calculation results CLKcal. However, from above-mentioned steps 124, 126, 128, 130, 132, it is obvious that only the optimum calculation result CLKbest and corresponding values M, N, R are finally recorded, wherein the values M, N, R are inputted into the clock generator 24 for control the actual pixel clock to equal the optimum calculation result CLKbest (step 136).
Because BIOS of the graphics card has a limited memory capacity equaling 64 k bytes, program codes of the BIOS are loaded into memory addresses ranging from C0000H to D0000H of the memory 14 when the computer device 10 is booting up. Concerning step 120, the program codes must include a power calculation for obtaining the necessary divisor 2R. Then, a division related to a dividend (the product Vco) and the divisor 2R is performed to figure out a quotient and a remainder. However, during the process of setting the pixel clock, the calculated remainder is actually discarded. That is, only the calculated quotient is reserved to set the calculation result CLKcal. As mentioned above, operation of the prior art corresponds to great computational complexity. Therefore, program code associated with the clock setting procedure demands a great amount of instructions so that the memory capacity of the BIOS 26 is seriously occupied. In other words, the BIOS 26 with a limited memory capacity is not capable of including additional program codes to expand functionality of the display driving circuit 16. In addition, CPU 12 of the computer device 10 requires a stack with a great capacity so that the CPU 12 can successfully push data onto the stack and pop data out of the stack when performing above-mentioned clock setting procedure.
It is well-known that certain segments of the memory 14 are reserved for special purposes. If the data pushed onto the stack occupies the reserved segments of the memory 14, the stored data absolutely overwrites data previously held in the reserved segments. Therefore, an unexpected crash may occur on the computer device 10. Otherwise, when the data pushed onto the stack occupies the reserved segments of the memory 14, and the CPU 12 stores data later to update information held in the reserved segments, it is obvious that the data previously pushed onto the stack are modified finally. Therefore, during the process of calculating the calculation result CLKcal, when the information held in the reserved segments is extracted from the stack, the erroneous data then affect the desired calculation result CLKcal. In addition, steps 124, 126 are respectively used to calculate the first difference D1 and the second difference D2. Then, the step 128 is executed to compare the first and second differences D1, D2. At the same time, step 130 utilizes the calculation result CLKcal to determine the optimum calculation result CLKbest so that step 126 is capable of calculating the second difference D2. Therefore, if the calculation result CLKcal is represented by 32 bits, not only is the above calculation complicated, but also the stack makes use of a great amount of capacities.